The invention relates to a junction field-effect transistor containing at least a gate electrode, a semiconductor region having at least a drain contact region disposed on a first surface of the semiconductor region and formed of a first conductivity type, a control region formed of a second conductivity type and an inner region formed of the first conductivity type. The transistor further has a source contact region formed of the first conductivity type, the control region and the inner region being at least partly disposed between the source contact region and the drain contact region.
Such a junction field-effect transistor is disclosed in International Patent Disclosures WO 97/23911 A1 and WO 98/49733 A1. Each of the two documents describes a normally on junction field-effect transistor (JFET) which can be used to control a current flow between two electrodes. In particular, with the aid of the JFET, the current is switched on and off or else limited to a maximum value. On the other hand, the JFET is able to take up the reverse voltage of more than 1000 V that arises in the reverse-biasing situation. Owing to the high breakdown strength of silicon carbide (SiC) the JFET is preferably composed of corresponding monocrystalline semiconductor material. The JFET contains a buried island region that functions as a control region and effects field shielding of one electrode.
In a unipolar transistor, such as the JFET, the dielectric strength is determined inter alia by the doping of an inner region that carries a large part of the reverse voltage in the reverse-biasing situation and carries the current in the forward-biasing situation. The inner region is also referred to as a drift zone. The higher the values that are to be assumed by the reverse voltage to be carried, the lower the doping of the inner regions must be chosen. On the other hand, in order to ensure, in the forward-biasing situation, that current is transported through the inner region in a manner as free from losses as possible, the doping should, by contrast, be as high as possible.
The contrary effects described mean, for example, that a power transistor realized in silicon, such as e.g. a voltage-controlled Si-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or else an Si-JFET, is usually realized only for a maximum reverse voltage of a few 100 V. When the doping is configured for a higher reverse voltage, the static on-state losses and, consequently, the risk of disruption of the transistor through overheating greatly rise.
Furthermore, German Patent DE 43 09 764 C2 (which corresponds to U.S. Pat. No. 5,438,215) discloses a normally off power MOSFET which can block a voltage of more than 1000 V. In order to reduce the forward resistance in the MOSFET, additional p-doped and n-doped zones are provided in the inner region, the zones having a higher doping concentration than the inner region. This results in suitability for a high reverse voltage in conjunction with low static on-state losses. In this case, the configuration features specified can only relate to a MOSFET. This is because, in contrast to a JFET, a MOSFET always requires a control oxide in order to influence the current flow. The specific properties of the control oxide, in particular the maximum permissible field strength, likewise have an influence on the maximum possible reverse voltage. In the MOSFET configuration, therefore, care must also be taken to ensure that impermissibly high field spikes are not produced in the control oxide in the reverse-biasing situation. This occasionally has the effect that the material properties of the semiconductor material can only be utilized in part, on account of the stipulations necessitated by the control oxide.
It is accordingly an object of the invention to provide a junction field-effect transistor with a more highly doped connecting region that overcomes the above-mentioned disadvantages of the prior art devices of this general type. The invention specifies a power transistor that is at the same time suitable for a high reverse voltage and, in addition, has low static losses in the forward-biasing situation. Furthermore, the intention is for the power transistor to manage without a control oxide.
With the foregoing and other objects in view there is provided, in accordance with the invention, a junction field-effect transistor. The JFET contains a semiconductor region having a first surface and a second surface opposite the first surface. The semiconductor region includes a drain contact region disposed at the first surface of the semiconductor region and formed of a first conductivity type; an inner region disposed above the drain contact region and formed of the first conductivity type; and a control region disposed above the inner region and formed of a second conductivity type. A gate electrode is disposed above the control region.
A source contact region is provided and is formed of the first conductivity type. The control region and the inner region are at least partly disposed between the source contact region and the drain contact region. A first connection region formed of the first conductivity type is provided. The first connection region has at least one inner part running within the semiconductor region substantially perpendicularly to the first surface. The first connection region is directly connected to the source contact region in a low-impedance manner and is doped more highly than the inner region. A second connection region formed of the second conductivity type and having at least one inner part running within the semiconductor region substantially perpendicularly to the first surface, is provided. The second connection region compensates for an influence of the first connection region in a reverse-biasing situation.
In this case, the invention is based on the insight that the bulk resistance in the inner region of the junction field-effect transistor (JFET) can be reduced by at least a first connecting region doped more highly than the inner region. The first connecting region has the same conductivity type as the inner region and it extends at least partly into the region of the JFET through which a current flows in the forward-biasing situation. In order to obtain the longest possible current path with a low bulk resistance, the first connecting region is directly connected to the source contact region. In this case, the connection is effected with a low impedance. For the current flowing between the source contact region and the drain contact region in the forward-biasing situation, this results in a path having distinctly lower losses than in the case of a current flow via the more lightly doped inner region.
In the reverse-biasing situation, a lower dielectric strength of the first connecting region, which is caused by the higher doping is nevertheless not realized. This is because the influence of the first connecting region is at least partly compensated for by the second connecting region having the second conductivity type. At a high reverse voltage, there are practically no longer any free charge carriers present in the inner parts of the first and second connecting regions. This is because they are completely depleted above a specific value of the reverse voltage, with the result that only the space charges remain. As a result, the equipotential lines of the electric field, above the reverse voltage value, run practically parallel to the first surface through the semiconductor region. Thus, an electric field distribution is established as if the connecting regions were actually not present. Consequently, reverse-biasing behavior of the JFET is not impaired by the above-described measure for reducing the bulk resistance in the forward-biasing situation. The maximum reverse voltage that can be carried by the JFET is determined according to the doping of the inner region, exactly as in the case of the prior art.
In the JFET, the current flow is controlled through at least one depletion layer between semiconductor regions having an opposite conductivity type. A control oxide is not necessary for this purpose. The field spikes in the control oxide that are possible in a MOSFET cannot occur, in principle, in the JFET.
A preferred embodiment relates to the configuration of the inner parts of the first and second connecting regions within the semiconductor region. Situated in the semiconductor region is a recess which, proceeding from a second surface of the semiconductor region, extends into the semiconductor region. In this case, the second surface is disposed on a side of the semiconductor region that is opposite to the first surface. By way of example, the recess may be etched in the form of a trench into the semiconductor region. The inner parts of the first and second connecting regions are introduced into the trench. This can be done either by way of epitaxial growth of undoped or only weakly doped layers with subsequent ion implantation or else by way of direct epitaxial growth corresponding to n-doped and p-doped layers. In accordance with the current flow between the source contact region and the drain contact region through the semiconductor region, both the trench and, situated in it, the inner parts of the first and second connecting regions run perpendicularly to the first surface of the semiconductor region.
Also advantageous is an embodiment of the junction field-effect transistor in which the at least one inner part of the first connecting region adjoins edges of the recess. In this case, the inner part of the first connecting region can be disposed in direct proximity both to the lateral edges and to the lower edge of the recess. As a result, the inner part of the first connecting region adjoins the inner region of the semiconductor region, which has the same conductivity type although in a weaker doping concentration. This results in a more favorable field distribution and better coupling than in the case of an embodiment in which the at least one inner part of the second connecting region adjoins edges of the recess.
An advantageous embodiment of the junction field-effect transistor is distinguished by the fact that for each inner part running perpendicularly to the first surface of the first connecting region there exists an inner part running parallel theretoxe2x80x94of the second connecting region. The effect achieved by this assignment is that the most optimal compensation possible of space charges within the two connecting regions takes place in the reverse-biasing situation. As a result, the advantageous course of the equipotential lines, the course being directed parallel to the first surface, is then established within the entire semiconductor region.
The aforesaid compensation of reciprocal space charges between the two connecting regions is additionally optimized in a further advantageous embodiment by the mutually assigned inner parts of the first and second connecting regions directly adjoining one another. The nearer the corresponding space charge zones having opposite polarity are to one another, the better the compensation.
In another advantageous refinement, the first connecting region extends as far as the drain contact region, which, for its part, adjoins the first surface of the semiconductor region. As a result, the drain contact region is also connected to the first connecting region in a low-impedance manner. The result is a continuous current path between the source contact region and the drain contact region, which has a higher doping and thus a lower bulk resistance than the inner region. The above-described reciprocal compensation of space charges between the first and the second connecting region results in that the reverse-biasing behavior is not impaired in this advantageous refinement either.
Also advantageous is an embodiment in which at least the inner part of the first connecting region has a doping concentration that at least largely corresponds to the breakdown charge of the semiconductor material used. In this connection, the breakdown charge is understood to be that space charge which is necessary in order that a maximum field strength forms at a p-n junction, the maximum field strength corresponding to the critical field strength of the semiconductor material used. If the field strength rises above this material-specific value of the critical field strength, then a so-called avalanche breakdown occurs. The above-mentioned term xe2x80x9cbreakdown chargexe2x80x9d is derived from this. The maximum field strength that forms is proportional to the doping concentration that determines the space charge. Therefore, the inner part of the first connecting region thus has its maximum permissible doping concentration precisely when it is doped in accordance with the critical field strength or, this being analogous thereto, in accordance with the breakdown charge. Since the drift resistance decreases with rising doping concentration, the minimum possible static on-state losses are also obtained with the above-mentioned doping concentration.
In an advantageous refinement of the junction field-effect transistor, at least the inner part of the second connecting region has a doping concentration that at least largely corresponds to that of the inner part of the first connecting region. The effect achieved by an identical doping concentration in both connecting regions is that, at maximum reverse voltage, each stationary space charge of one connecting region can be assigned a space charge zone of the other connecting region. This results in the greatest possible reciprocal compensation.
In another advantageous embodiment, the junction field-effect transistor is at least partly composed of a semiconductor material that has an energy gap of at least 2 eV. Examples of such a semiconductor material are diamond, gallium nitride (GaN), indium phosphide (InP) and silicon carbide (SiC). The latter, especially, is particularly well suited on account of the extremely low intrinsic charge carrier concentration (=charge carrier concentration without doping) and the very low material-specific on-state losses. The above-mentioned semiconductor materials additionally have a distinctly higher breakdown strength in comparison with the xe2x80x9cuniversal semiconductorxe2x80x9d silicon (Si). Therefore, given an otherwise identical geometry, a JFET realized with one of the abovementioned semiconductors can carry a higher reverse voltage than an Si-JFET. The preferred semiconductor material is silicon carbide, in particular monocrystalline silicon carbide of the 3C, 4H, 6H or 15R polytype, since SiC has outstanding electronic and thermal properties.
In a junction field-effect transistor made of silicon carbide, the inner part of the first connection region preferably has a doping concentration of at most 1xc2x71013 cmxe2x88x922. In this case, the value is related to a fictitious area disposed perpendicular to the first surface.
In principle, the junction field-effect transistor can, however, also be realized with the semiconductor material silicon. Silicon is a highly available semiconductor material that can be obtained in extremely good monocrystalline quality. Moreover, the power loss that can be attained with silicon for a predetermined maximum reverse voltage is small enough for many applications of power electronics.
In the case of a realization of the junction field-effect transistor in silicon, the first connecting region has a preferred doping concentration of at most 1.5xc2x71012 cmxe2x88x922. This concentration is once again related to a fictitious area that runs perpendicularly to the first surface.
Preference is given to an embodiment in which the control region extends along a second surface of the semiconductor region. The second surface is situated on a side of the semiconductor region that is opposite to the first surface.
An advantageous embodiment of the junction field-effect transistor is one in which the gate electrode makes ohmic contact both with the control region and with the second connecting region. This opens up the possibility of influencing the current flow and also the field distribution by a single control potential present at the common gate electrode.
The junction field-effect transistor is advantageously configured in such a way that a layer stack containing an outer part of the first connecting region, the source contact region and an outer part of the second connecting region is disposed on the semiconductor region above the control region. In this case, the outer part of the first connecting region adjoins the semiconductor region. Furthermore, the layer stack is advantageously constructed in such a way that a projection of the control region and a projection of the outer part of the second connecting region at least partly overlap. In this case, a common direction of the projections runs perpendicularly to the first surface. In the region of overlap, a channel zone is then produced within the source contact region and the outer part of the first connecting region, via which channel zone the current flow can be controlled. Space charge zones (=depletion layer zones) which bound the channel zone form at p-n junctions between the outer part of the second connecting region and the source contact region and also between the control region and the outer part of the first connecting region. The extent of the space charge zones and thus the current flow can be influenced by a control potential present at the second connecting region and the control region.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a junction field-effect transistor with more highly doped connecting region, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.